Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device for generating an internal clock signal and a method for operating the same.
In general, semiconductor devices including Double Data Rate Synchronous DRAMs (DDR SDRAMs) receive an external clock signal to generate an internal clock signal, and use the internal clock signal as a reference signal for controlling a variety of operation timings in the semiconductor devices. Therefore, the semiconductor devices include an internal clock signal generation circuit configured to generate an internal clock signal. Examples of the internal clock signal generation circuit may include a Delay Locked Loop (DLL) and a Phase Locked Loop (PLL). Hereafter, the DLL is described as a representative example for convenience of explanation.
FIG. 1 is a block diagram of a conventional DLL.
Referring to FIG. 1, the DLL includes a variable delay unit 110, a delay replica modeling unit 120, a phase detection unit 130, a control signal generation unit 140, a delay line control unit 150, and a locking detection unit 160.
The variable delay unit 110 is configured to delay an external clock signal CLK_EXT by a time period corresponding to one of the delay control signals SH0 to SHN to generate a DLL clock signal CLK_DLL. The DLL clock signal generated in such a manner is inputted to the delay replica modeling unit 120. The delay replica modeling unit 120 includes a clock path and a data path modeled in the semiconductor device. The DLL clock signal CLK_DLL is delayed by a time period modeled in the delay replica modeling unit 120, and becomes a feedback clock signal CLK_FED. The phase detection unit 130 is configured to compare the phase of the external clock signal CLK_EXT with that of the feedback clock signal CLK_FED, and to generate a phase detection signal DET_PHS corresponding to the comparison result.
The control signal generation unit 140 is configured to generate an up/down control signal CTR_UD in response to the phase detection signal DET_PHS. The delay line control unit 150 is configured to generate the delay control signals SH0 to SHN in response to the up/down control signal CTR_UD. The generated delay control signals SH0 to SHN control a delay amount reflected in the variable delay unit 110. The locking detection unit 160 is configured to generate a locking detection signal DET_LOC in response to the phase detection signal DET_PHS. The locking detection signal DET_LOC is activated when the locking operation of the DLL has been completed.
Through such a configuration, the DLL generates one of the delay control signals SH0 to SHN such that the phase of the external clock signal CLK_EXT becomes identical to that of the feedback clock signal CLK_FED, and then generates a DLL clock signal CLK_DLL corresponding to the delay control signal. Such a state in which the two phases become identical is referred to as ‘locking’. The DLL clock signal CLK_DLL generated after the locking operation has been completed is transferred to a circuit configured to output data, and the data is synchronized with the transferred DLL clock signal CLK_DLL and then outputted. The data which is synchronized with the DLL clock signal CLK_DLL and outputted operates as if the data is synchronized with the external clock signal CLK_EXT and then outputted.
Meanwhile, the duty cycle ratios of the external clock signal CLK_EXT inputted to the DLL, the outputted DLL clock signal CLK_DLL, and the feedback signal CLK_FED may be distorted depending on environmental elements reflected in the DLL, such as fabrication processes, supplied voltages, and temperature. When the duty cycle ratios of the clock signals are distorted, the performance of the DLL may be degraded. Furthermore, since such environmental elements may change a variety of delay times reflected in the DLL, the DLL may not perform a desired operation. Therefore, to compensate for the distorted duty cycle ratios of the clock signals or for the changed delay times, a circuit capable of monitoring environmental elements reflected in the circuit is preferentially required.